High definition television receiver

ABSTRACT

A HDTV receiver which is improved in its overall performance and is simplified in its configuration, by improving a symbol timing restoring circuit, includes a tuner for selecting a necessary channel from input signals via an antenna, an IF processing &amp; carrier restoring portion for performing an IF process &amp; carrier restoration from the output of the tuner, an analog-to-digital converter (ADC) for converting the output of the IF processing &amp; carrier restoring portion into a digital signal, a timing restoring portion for restoring a timing from the output of the ADC, a 2:1 down-sampler for 2:1 down-sampling the output of the ADC, a sync detector for detecting a sync from the output of the 2:1 down-sampler, a channel equalizer for performing a channel equalization from the output of the 2:1 down-sampler, a phase controller for correcting the phase error from the output of the channel equalizer, an optimal viterbi decoder for performing a viterbi decoding operation from the output of the phase controller, a deinterleaver for dissipating the output of the optimal viterbi decoder in order to enhance the correction capability due to burst errors, an error controller for performing a Reed-Solomon decoding operation with respect to the output of the deinterleaver, and a derandomizer for releasing the output of the error controller and restoring a signal randomly formed at a transmission port reversely.

BACKGROUND OF THE INVENTION

The present invention relates to a high definition television (HDTV)receiver, and more particularly, to a HDTV receiver which is improved inits overall performance and is simplified in its configuration, byimproving a symbol timing restoring circuit.

FIG. 1 is a block diagram of a conventional 8-vestigial sideband (VSB)receiver, in which a high-frequency signal input from an antenna (ANT)is demodulated and is carrier-restored when a channel is a selected in atuner 1 and a signal having a central frequency of 44 MHz isautomatic-gain controlled and IF-bandpass filtered in an IF processor &carrier restoring portion 2.

This signal is digitally sampled in an analog-to-digital conventer (ADC)3 and precise symbol timing is detected by a timing restoring portion 4,thereby controlling the timing of ADC 3.

The output of ADC 3 is also input to a sync detector 5 to detect a datasegment sync from a data segment sync pattern (FIG. 3A) and to detect afield sync from a field sync pattern being in the first line of atransmission format.

At this time, the data segment sync and field sync detected in syncdetector 5 are used as the control signals of subsequent blocks 7through 16.

NTSC (National Television System Committee) interference detector 7receives a signal passing through a post-comb filter 6 and a signal notpassing therethrough and determines whether there is an identicalchannel interference with that of NTSC or not, to then transmit a combcontrol signal SC1.

If there is no NTSC identical channel interference, the signal notpassing through post-comb filter 6 is selected by a multiplexer 8. Achannel equalizer 9 equalizes the incoming signal which is set to 8levels to remove the intersymbol interference due to a ghost generatedat the channel.

Also, a phase corrector 10 corrects the phase error remaining aftersignal-processing, setting the incoming signal to 8 levels. An optimalviterbi decoder 11 performs a 4-state viterbi decoding operation and thedecoded output is output through multiplexer 13.

If there is NTSC identical channel interference, the output of post-combfilter 6 is selected as the output of multiplexer 8. At this time,post-comb filter 6 subtracts data delayed for 12 symbol period from thecurrent data.

Therefore, the original 8 level data becomes 15 level data. The NTSCidentical channel interference is removed. At this time, channelequalizer 9 and phase controller 10 operate assuming that the incomingsignal is 15 level data, and multiplexer 13 selects and outputs theoutput of a partial response (PR) viterbi decoder 12.

PR viterbi decoder 12, an 8-state decoder, has much more complexstructure than that of optimal viterbi decoder 11.

The output of multiplexer 13 is dissipated in order to enhance thecorrection capability for burst errors in a deinterleaver 14. An errorcontroller 15 performs a Reed-Solomon decoding operation.

Also, a derandomizer 16 releases a signal randomly formed in atransmission port reversely. Timing restoring portion 4 is constitutedby a data segment sync detector 4 a and a phase locked loop (PLL) 4 b,as shown in FIG. 2. The digitally converted signal is concurrentlyoutput to data segment sync detector 4 a and PLL 4 b.

At this time, data segment sync detector 4 a detects a data segmentsync, based on the data pattern “1001” for 4 symbol period of 2 levelsshown in FIG. 3A.

PLL 4 b detects the phase error for the timing from a data segment syncpattern. The output of a phase detector is as shown as FIG. 3B,digitally, and as FIG. 3C, analogically.

The position of a sampling point 4 shown in FIG. 3C is a zero-crossingpoint, and a symbol timing is detected using the zero-crossing point.

However, the aforementioned conventional art adopting a post-comb filterfor reducing the NTSC identical channel interference has a very complexconfiguration.

SUMMARY OF THE INVENTION

To solve these problems, it is an object of the present invention toprovide a HDTV receiver, which allows a better symbol timing restorationeven if there is an NTSC identical channel interference, by improving asymbol timing restoring circuit, and which is simplified in itsconfiguration, by eliminating a post-comb filter.

To accomplish the above object, there is provided a HDTV receivercomprising: a tuner for selecting a necessary channel from input signalsvia an antenna; an IF processing & carrier restoring portion forperforming an IF process & carrier restoration from the output of thetuner; an analog-to-digital converter (ADC) for converting the output ofthe IF processing & carrier restoring portion into a digital signal; atiming restoring portion for restoring a timing from the output of theADC; a 2:1 down-sampler for 2:1 down-sampling the output of the ADC; async detector for detecting a sync from the output of the 2:1down-sampler; a channel equalizer for performing a channel equalizationfrom the output of the 2:1 down-sampler; a phase controller forcorrecting the phase error from the output of the channel equalizer; anoptimal viterbi decoder for performing a viterbi decoding operation fromthe output of the phase controller; a deinterleaver for dissipating theoutput of the optimal viterbi decoder in order to enhance the correctioncapability due to burst errors; an error controller for performing aReed-Solomon decoding operation with respect to the output of thedeinterleaver; and a derandomizer for releasing the output of the errorcontroller and restoring a signal randomly formed at a transmission portreversely.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore apparent by describing in detail a preferred embodiment thereofwith reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional HDTV receiver;

FIG. 2 is a detailed block diagram of a timing restoring portion shownin FIG. 1;

FIGS. 3A through 3C are timing charts shown in FIG. 2;

FIG. 4 is a block diagram of a HDTV receiver according to the presentinvention; and

FIG. 5 is a detailed block diagram of a timing restoring portion shownin FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

As shown in FIG. 4, the HDTV receiver according to the present inventionhas a simpler configuration than the conventional system in thatpost-comb filter 6, NTSC interference detector 7, multiplexer 8, PRviterbi decoder 12 and multiplexer 13 are eliminated from theconventional one. Channel equalizer 9 and phase corrector 10 of theconvention system correspond to channel equalizer 107 and phasecontroller 108 of the present invention, respectively. Timing restoringportion 4 of the convention system corresponds to a new timing restoringportion 104 of the present invention, so that a symbol timingrestoration is performed well even in the case of the NTSC identicalchannel interference.

As shown in FIG. 5, timing restoring portion 104 includes an FIR filter113 for filtering only the signal of a necessary symbol rate among thesignals passing through ADC 103, a phase error detector 114 fordetecting an phase error (ek) from the output of FIR filter 113, adigital-to-analog converter (DAC) 115 for converting again the output ofphase error detector 114 into an analog signal, a lowpass filter 116 forlowpass-filtering the output of DAC 115, and a voltage controlledoscillator 117 for varying an oscillated frequency according to theoutput of lowpass filter 116 to supply a signal required in ADC 103.

At this time, phase error detector 114 is constituted by ½ symbol ratedelays 114 a and 114 b for delaying the output of FIR filter 113 by ½symbol rate, an adder 114 c for adding the output of FIR filter 113 withthe output of ½ symbol rate delay 114 b, and a multiplier 114 d formultiplying the output of adder 114 c with the output of ½ symbol ratedelay 114 a to output a phase error (ek).

In the present invention having the aforementioned configuration, theoperation of a tuner 101 and an IF processing & carrier restoringportion is the same as that of the conventional art. ADC 103 uses aclock of 21.52 MHz for over-sampling twice the symbol rate with asampling clock, which is because the data twice over-sampled is requiredin timing restoring portion 104.

The signal restored from timing restoring portion 104 is directlysupplied to 2:1 down-sampler 105, and 2:1 down-sampler 105 samples onlythe data of a desired symbol rate. A sync detector 106 detects a datasegment sync and a data field sync.

A channel equalizer 107 to which only 8 level data is applied equalizesin accordance therewith. Also, phase controller 108 and optimal viterbidecoder 109 to which only 8 level data are applied, operate irrespectiveof 15 level data.

The operations of deinterleaver 110, error controller 111 andderandomizer 112 will be omitted here, since the respective elementsoperate in the same manner as that of the corresponding elements of theconventional system.

The signal passing through ADC 103 undergoes a bandpass filteringoperation of central 5.38 MHz (=½T, here, 1/T is symbol rate) in FIRfilter 113 of timing restoring portion 104.

The output of FIR filter 113 is delayed in ½ symbol rate delays 114 aand 114 b by ½ symbol rate. The output of ½ symbol rate delay 114 b andthe output of FIR filter 113 is added in an adder 114 c. The addedoutput and the output of ½ symbol rate delay 114 a is multiplied in amultiplier 114 d to then output a phase error (ek).

A phase error (ek) is converted into an analog signal in DAC 115 and islowpass-filtered in a low-pass in lowpass filter 16. Then,voltage-controlled oscillator (VC) 117 supplies a clock required for DAC103.

In other words, the signal passing through timing restoring portion 104becomes a symmetric IF bandpass filtered signal of central 5.38 MHz. Azero crossing always occurs at a position of odd number times of T/2.

As described above, according to the the present invention, a symboltiming restoration is done well even if there is an NTSC identicalchannel interference, by improving a symbol timing restoring circuit.Also, based on the improved symbol timing restoring circuit, a post-combfilter can be eliminated, which considerably simplifies the overallcircuit configuration.

What is claimed is:
 1. A An HDTV receiver comprising: a tuner forselecting a necessary channel from input signals via an antenna; an IFprocessing & carrier restoring portion for performing an IF process &carrier restoration from the an output of said tuner; ananalog-to-digital converter (ADC) for converting the an output of saidIF processing & carrier restoring portion into a digital signal; atiming restoring portion for restoring said timing from the output ofsaid ADC; a 2:1 down-sampler for 2:1 down-sampling the an output of saidADC; a sync detector for detecting a sync from the an output of the 2:1down-sampler; a channel equalizer for performing a channel equalizationfrom the an output of the 2:1 down-sampler; a phase controller forcorrecting the a phase error from the an output of the channelequalizer; an optimal viterbi decoder for performing a viterbi decodingoperation from the an output of said phase controller; a deinterleaverfor dissipating the an output of said optimal viterbi decoder in orderto enhance the correction a capability due to correct burst errors; anerror controller for performing a Reed-Solomon decoding operation withrespect to the an output of said deinterleaver; and a derandomizer forreleasing the an output of said error controller and restoring a signalrandomly formed at a transmission port reversely.
 2. A An HDTV receiveras claim 1, where said timing restoring portion comprises: an FIR filterfor filtering only the signal of a necessary symbol rate among the aplurality of signals passing through said ADC; a phase error detectorfor detecting an a phase error (ek) from the output of said FIR filter;a digital-to-analog converter (DAC) for converting again the output ofsaid phase error detector into an analog signal; a lowpass filter forlowpass-filtering the output of said DAC; and a voltage controlledoscillator for varying an oscillated frequency according to the outputof said lowpass filter to supply a signal required in said ADC.
 3. A AnHDTV receiver as claim 1 2, where said phase error detector comprises:first and second ½ symbol rate delays for delaying the output of saidFIR filter by ½ symbol rate; an adder for adding the outputs of saidsecond ½ symbol rate delay; and a multiplier for multiplying the outputof said adder with the output of said first ½ symbol rate delay tooutput a phase error (ek).
 4. A digital television receiver comprising:a tuner for selecting a channel from input signals; an IF processingportion for performing an IF process from an output signal of the tuner;an analog-to-digital converter coupled to the IF processing portion andconverting an output signal from the IF processing portion into adigital signal; a timing restoring portion coupled to theanalog-to-digital converter and restoring a timing from an output signalof the analog-to-digital converter; an N:M sampler coupled to theanalog-to-digital converter and N:M sampling the output signal of theanalog-to-digital converter, where N and M are integers and N is greaterthan M; a sync detector coupled to the N:M sampler and detecting a syncfrom an output signal of the N:M sampler; a channel equalizer coupled tothe N:M sampler and performing a channel equalization from the outputsignal of the N:M sampler; a phase controller coupled to the channelequalizer and correcting a phase error from an output of the channelequalizer; a deinterleaver coupled to the phase controller and enhancingan error correction capability; an error controller coupled to thedeinterleaver and performing a decoding operation with respect to anoutput signal of the deinterleaver; and a derandomizer coupled to theerror controller and releasing an output signal of the error controllerand restoring a randomly formed signal.
 5. The digital televisionreceiver according to claim 4, wherein the tuner includes the IFprocessing portion.
 6. The digital television receiver according toclaim 4, further comprising a carrier restoration portion performingcarrier restoration from the output signal of the tuner.
 7. The digitaltelevision receiver according to claim 4, wherein the N:M samplerincludes a 2:1 down sampler.
 8. The digital television receiveraccording to claim 4, further comprising an optimal viterbi decodercoupled to the phase controller and performing a decoding operation fromthe output signal of the phase controller.
 9. The digital televisionreceiver according to claim 8, wherein the deinterleaver dissipates anoutput signal of the optimal viterbi decoder.
 10. The digital televisionreceiver according to claim 4, wherein the timing restoring portioncomprises: an FIR filter for filtering a signal of a selected symbolrate among a plurality of signals input to the timing restoring portion;a phase error detector for detecting a phase error from an output signalof said FIR filter; a digital-to-analog converter for converting outputsignal of the phase error detector into an analog signal; a low passfilter for low-pass filtering an output signal of the digital-to-analogconverter; and a voltage controlled oscillator for varying anoscillating frequency according to an output signal of the low passfilter to supply a signal required in the analog-to-digital converter.11. The digital television receiver according to claim 10, wherein thephase error detector comprises: first and second {fraction (1/2)} symbolrate delays for delaying the output signal of the FIR filter by{fraction (1/2)} symbol rate; an adder for adding the output signal ofthe FIR filter and an output signal of the second {fraction (1/2)}symbol rate delay; and a multiplier for multiplying an output signal ofthe adder with an output signal of the first {fraction (1/2)} symbolrate delay to output the phase error.
 12. The digital televisionreceiver of claim 4, wherein the timing restoring portion restoressymbol timing to the output signal of the analog-digital converter. 13.A digital television receiver comprising: an input unit receiving atelevision signal and generating a digital signal through at least a 2:1upsampling; a timing restoring portion restoring a timing from theupsampled digital signal; a down-sampler for at least 2:1 down samplingthe upsampled digital signal and outputting a down-sampled signal; async detector detecting a sync from the down-sampled signal of thedown-sampler; a channel equalizer performing a channel equalization fromthe down-sampled signal of the down-sampler and outputting a channelequalized signal; a phase controller correcting a phase error from thechannel equalized signal of the channel equalizer and outputting a phasecontrolled signal; a deinterleaver coupled to the phase controller andenhancing an error correction capability and outputting a deinterleavedsignal; an error controller performing a decoding operation with respectto the deinterleaved signal of the deinterleaver and outputting adecoded signal; and a derandomizer releasing the decoded signal of theerror controller and restoring a randomly formed signal.
 14. The digitaltelevision receiver according to claim 13, wherein the input unitcomprises: a tuner selecting a channel from input signal via an antenna;an IF processing portion for performing an IF process from an outputsignal of the tuner; a carrier restoring portion for performing acarrier restoration from the output signal of the tuner; and ananalog-to-digital converter converting an output signal of the IFprocessing portion into the digital signal.
 15. The digital televisionreceiver according to claim 14, wherein the timing restoring portioncomprises: an FIR filter for filtering a signal of a selected symbolrate among a plurality of signals input to the timing restoring portion;a phase error detector for detecting a phase error from an output signalof said FIR filter; a digital-to-analog converter for converting outputsignal of the phase error detector into an analog signal; a low passfilter for low-pass filtering an output signal of the digital-to-analogconverter; and a voltage controlled oscillator for varying anoscillating frequency according to an output signal of the low passfilter to supply a signal required in the analog-to-digital converter.16. The digital television receiver according to claim 15, wherein thephase error detector comprises: first and second {fraction (1/2)} symbolrate delays for delaying the output signal of the FIR filter by{fraction (1/2)} symbol rate; an adder for adding the output signal ofthe FIR filter and an output signal of the second {fraction (1/2)}symbol rate delay; and a multiplier for multiplying an output signal ofthe adder with an output signal of the first {fraction (1/2)} symbolrate delay to output the phase error.
 17. The digital televisionreceiver of claim 14, wherein the timing restoring portion restoressymbol timing to the upsampled digital signal.
 18. The digitaltelevision receiver of claim 17, wherein the timing restoring portioncomprises: a filter for filtering a signal of a selected symbol rateamong a plurality of signals input to the filter; a phase error detectorfor detecting a phase error in an output signal of said filter; a lowpass filter for low-pass filtering an output signal of the phase errordetector; and a voltage controlled oscillator for varying an oscillatingfrequency supplied to the low pass filter to supply a signal required inthe analog-to-digital converter.
 19. The digital television receiveraccording to claim 13, wherein the input unit comprises: a tunerselecting a channel from an input signal via an antenna; and an IFprocessing portion for performing an IF process from an output signal ofthe tuner.
 20. The digital television receiver according to claim 13,wherein the input unit comprises: a tuner selecting a channel from inputsignal via an antenna; an IF processing portion for performing an IFprocess from an output signal of the tuner; and carrier restoringportion for performing a carrier restoration from the output signal ofthe tuner.
 21. The digital television receiver according to claim 13,further comprising an optimal viterbi decoder coupled to the phasecontroller and performing a decoding operation from the output signal ofthe phase controller.
 22. The digital television receiver according toclaim 21, wherein the deinterleaver dissipates an output signal of theoptimal viterbi decoder.
 23. The digital television receiver of claim13, wherein the timing restoring portion restores symbol timing to theupsampled digital signal.
 24. The digital television receiver of claim13, wherein the television signal is an 8-VSB digital television signal.25. The digital television receiver of claim 24, wherein the input unitalso receives an NTSC television signal on a same channel as the 8-VSBdigital television signal, and further wherein the timing restoringportion restores symbol timing to the upsampled digital signal.
 26. Adigital television receiver, comprising: a tuner for selecting onechannel of a plurality of channels; an IF processor coupled to an outputof said tuner for IF processing an output signal of the tuner; ananalog-to-digital converter coupled to an output of the IF processor forconverting an output signal of the IF processor to a digital signal; atiming restoring portion for controlling timing of the analog-to-digitalconverter; an N:M downsampler coupled to the output of theanalog-to-digital converter for sampling the digital signal, wherein Nand M are integers and N is greater than M; a channel equalizer coupledto an output of the N:M downsampler for channel equalizing the digitalsignal; a phase controller coupled to an output of the channel equalizerfor correcting a phase error in the digital signal; a deinterleavercoupled to an output of the phase controller for enhancing a capabilityto correct burst errors in the digital signal; an error controllercoupled to an output of the deinterleaver for decoding the digitalsignal; and a derandomizer coupled to an output of said error controllerfor derandomizing the digital signal.
 27. The digital televisionreceiver of claim 26, wherein the tuner receives an 8-VSB digitaltelevision signal in the selected channel.
 28. The digital televisionreceiver of claim 27, wherein the tuner also receives an NTSC televisionsignal on a same channel as the 8-VSB digital television signal.
 29. Thedigital television receiver of claim 26, wherein the timing restorationportion restores symbol timing to the digital signal.
 30. The digitaltelevision receiver of claim 26, wherein the timing restoration portioncomprises: a filter coupled to the output of the analog-to-digitalconverter for filtering a signal of a selected symbol rate among aplurality of signals input to the filter; a phase error detector fordetecting a phase error in an output signal of said filter; a low passfilter for low-pass filtering an output signal of the phase errordetector; and a voltage controlled oscillator coupled to an output ofthe low pass filter and providing a signal for controlling timing of theanalog-to-digital converter.